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  • Jitter and Spur Minimization in Fractional-N Digital Frequency Synthesizers

    Modeling, Simulation, Analysis, and Design Methodologies

    Series series Engineering (R0)
    This book presents a rigorous and practically grounded treatment of jitter and spur minimization in fractional-N digital phase locked loops (DPLLs), addressing one of the most critical challenges in modern frequency synthesis. Bridging the gap between theoretical analysis and design practice, it introduces a unified framework for modeling quantization and nonlinear effects in time-to-digital ... Read more

    $116.09 USD