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  • A Machine Learning based Pairs Trading Investment Strategy

    Series series Intelligent Technologies and Robotics (R0)
    This book investigates the application of promising machine learning techniques to address two problems: (i) how to find profitable pairs while constraining the search space and (ii) how to avoid long decline periods due to prolonged divergent pairs. It also proposes the integration of an unsupervised learning algorithm, OPTICS, to handle problem (i), and demonstrates that the suggested technique ... Read more

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  • Portfolio Optimization Using Fundamental Indicators Based on Multi-Objective EA

    Series series Engineering (R0)
    This work presents a new approach to portfolio composition in the stock market. It incorporates a fundamental approach using financial ratios and technical indicators with a Multi-Objective Evolutionary Algorithms to choose the portfolio composition with two objectives the return and the risk. Two different chromosomes are used for representing different investment models with real constraints ... Read more

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  • Analog Integrated Circuit Design Automation

    Placement, Routing and Parasitic Extraction Techniques

    Series series Engineering (R0)
    This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template ... Read more

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  • Analog IC Placement Generation via Neural Networks from Unlabeled Data

    Series series Computer Science (R0)
    In this book, innovative research using artificial neural networks (ANNs) is conducted to automate the placement task in analog integrated circuit layout design, by creating a generalized model that can generate valid layouts at push-button speed. Further, it exploits ANNs’ generalization and push-button speed prediction (once fully trained) capabilities, and details the optimal description of the ... Read more

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  • Logarithmic Voltage-to-Time Converter for Analog-to-Digital Signal Conversion

    Series series Engineering (R0)
    This book presents a novel logarithmic conversion architecture based on cross-coupled inverter. An overview of the current state of the art of logarithmic converters is given where most conventional logarithmic analog-to-digital converter architectures are derived or adapted from linear analog-to-digital converter architectures, implying the use of analog building blocks such as amplifiers. The ... Read more

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  • Parallel Genetic Algorithms for Financial Pattern Discovery Using GPUs

    Series series Engineering (R0)
    This Brief presents a study of SAX/GA, an algorithm to optimize market trading strategies, to understand how the sequential implementation of SAX/GA and genetic operators work to optimize possible solutions. This study is later used as the baseline for the development of parallel techniques capable of exploring the identified points of parallelism that simply focus on accelerating the heavy duty ... Read more

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  • Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects

    Series series Engineering (R0)
    This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit’s performance. The discussion also includes ... Read more

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  • AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing

    Series series Engineering (R0)
    This work addresses the research and development of an innovative optimization kernel applied to analog integrated circuit (IC) design. Particularly, this works describes the modifications inside the AIDA Framework, an electronic design automation framework fully developed by at the Integrated Circuits Group-LX of the Instituto de Telecomunicações, Lisbon. It focusses on AIDA-CMK, by enhancing ... Read more

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  • Tunable Low-Power Low-Noise Amplifier for Healthcare Applications

    Series series Engineering (R0)
    This book consists of the research, design and implementation, from sizing to layout with parasitic extraction and yield estimation, of a low-power, low-noise amplifier for biomedical and healthcare applications of bio-potential signals, particularly focusing on the electromyography and electrooculography. These signals usually operate in different broadbands, yet follow an impulse-shape ... Read more

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  • Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies

    Series series Engineering (R0)
    This book presents a new methodology with reduced time impact to address the problem of analog integrated circuit (IC) yield estimation by means of Monte Carlo (MC) analysis, inside an optimization loop of a population-based algorithm. The low time impact on the overall optimization processes enables IC designers to perform yield optimization with the most accurate yield estimation method, MC ... Read more

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  • Electronic Design Automation of Analog ICs combining Gradient Models with Multi-Objective Evolutionary Algorithms

    Series series Engineering (R0)
    This book applies to the scientific area of electronic design automation (EDA) and addresses the automatic sizing of analog integrated circuits (ICs). Particularly, this book presents an approach to enhance a state-of-the-art layout-aware circuit-level optimizer (GENOM-POF), by embedding statistical knowledge from an automatically generated gradient model into the multi-objective multi-constraint ... Read more

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  • A New Family of CMOS Cascode-Free Amplifiers with High Energy-Efficiency and Improved Gain

    Series series Engineering (R0)
    This book addresses the need for energy-efficient amplifiers, providing gain enhancement strategies, suitable to run in parallel with lower supply voltages, by introducing a new family of single-stage cascode-free amplifiers, with proper design, optimization, fabrication and experimental evaluation. The authors describe several topologies, using the UMC 130 nm CMOS technology node with standard-VT ... Read more

    $89.09 USD