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  • A Pipelined Multi-core MIPS Machine

    Hardware Implementation and Correctness Proof

    by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul ...
    Series series Computer Science (R0)
    This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.The book contains the first correctness proofs for both the gate level implementation of a multi-core ... Read more

    $49.49 USD